1. Field of the Invention
The present invention relates in general to a method for forming a trench top isolation layer. More particularly, it relates to a semiconductor device having a trench top oxide (TTO) and the method for forming the same.
2. Description of the Related Art
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones. In order to increase integrity of integrated circuits, the semiconductor industry in general is being driven to decrease the size of the semiconductor devices located on integrated circuits.
Semiconductor memory devices are one of the semiconductor products widely applied in electronic systems for storing data, and one common type of semiconductor memory is dynamic random access memory (DRAM). Typically, a DRAM cell includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations.
In order to decrease the size of the semiconductor memory devices, a vertical access transistor technology is developed. In such a technology, the storage capacitor is formed in the lower portion of the trench, and the access transistor is formed in the upper portion of the trench. In addition, a thick dielectric layer called trench top oxide (TTO) is formed between the capacitor and the transistor for electrical isolation therebetween.
FIG. 1 is a cross-section showing a conventional semiconductor device having a trench top isolation layer. The semiconductor device includes a substrate 100, such as a silicon substrate, having a deep trench 103 formed by etching the substrate 100 using a masking layer 105 as a hard mask. The masking layer 105 includes a pad oxide layer 102 and an overlying nitride layer 104. A trench capacitor (not shown) is disposed in the lower portion of the trench 103. A collar insulating layer 106, such as silicon oxide, is disposed overlying the trench capacitor and over the sidewall of the lower portion of the trench 103.
A conductive layer 108, such as a polysilicon layer, is disposed overlying the trench capacitor and protrudes the collar insulating layer 106. Another conductive layer 112, such as a polysilicon layer, is disposed on the conductive layer 108 and covers the collar insulating layer 106.
A buried strap 110 is formed in the substrate 100 near the upper portion of the collar insulating layer 106 to serve as a drain region for the subsequent vertical transistor. The drain region electrically connects with the trench capacitor through the conductive layers 108 and 112. In general, the buried strap 110 is formed by diffusing the dopant in a doped dielectric layer (not shown) into the substrate 100 by a drive-in process.
A TTO layer 114, such as tetraethyl orthosilicate (TEOS) oxide, is disposed on the conductive layer 112 for electrical isolation between the trench capacitor and the subsequent vertical transistor. Typically, the formation of the TTO layer 114 includes the following steps. First, a conformable silicon oxide layer is formed on the masking layer 105 and the inner surface of the trench 103 (overlying the conductive layer 112) by high-density plasma chemical vapor deposition (HDPCVD), wherein the bottom of the silicon oxide layer in the trench 103 is thicker than that over the sidewall of the trench 103. Thereafter, the silicon oxide layer on the masking layer 105 is removed by polishing and then that over the sidewall of the trench 103 is removed by wet chemical etching to leave the bottom portion of the silicon oxide layer in the trench 103. After wet chemical etching, however, the remaining silicon oxide layer serving as a TTO layer is dished at its middle portion, as shown in the FIG. 1, causing poor edge uniformity. The non-uniform TTO layer 114 degrades the insulating property and reduces reliability of the semiconductor device.